Evaluation of FlipFET™ Reliability Based on Solder Fatigue Modeling and a Simulated Design of Experiment
1025 Elkton Drive
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International Rectifier Corporation
Holland Road, Hurst Green
Oxted, Surrey RH8 9BB UK
44 (0) 1883 733222
A previously validated solder fatigue model has been used to evaluate and optimize the mechanical reliability of a the International Rectifier wafer level packaged MOSFET referred to as FlipFET.. This has been accomplished through a simulated design of experiment (DOE) which bounds the range of design parameters and thermal profiles that the device would typically encounter in an end user’s thermal cycling reliability qualification. A statistical analysis of the DOE results has been used to evaluate the significance of the design parameters and their interactions.
The simulated DOE consists of a full-factorial experiment containing five factors at two levels each. In particular, passivation opening (i.e., solderable surface), assembled chip stand-off, substrate thickness and conductor thickness have been evaluated for both –40/125C and – 55/150C thermal profiles. The response of the DOE is the predicted solder fatigue life based on nonlinear finite element analyses in conjunction with a previously published fatigue correlation. The solder fatigue life is expressed in terms of the Weibull life based on a two-parameter Weibull distribution. The results of the DOE have been used to quantify the solder fatigue life of the device, and have served as input to a statistical analysis used to evaluate the significance of first order effects and second order interactions. Results show that while passivation opening and stand-off are statistically significant factors affecting fatigue life, substrate and conductor thickness are not significant. Furthermore, no significance was observed for any of the interactions within the set limits of the DOE.
For the complete document, please contact Hank Carey at email@example.com or 719-533-1030 ext121