Flip Chip Reliability Modeling Based on Solder Fatigue as Applied to Flip Chip on Laminate Assemblies

  • Scott Popelar
    IC Interconnect
    1025 Elkton Drive
    Colorado Springs, CO 80907
    719-533-1030
    Michael Roesch
    Hewlett-Packard Co.
    1501 Page Mills Road, MS 6U-A
    Palo Alto, CA 94304
    650-857-7490

    Abstract

    In order to successfully implement reliable flip chip packaging technology it is desirable to ensure solder fatigue as the limiting mechanical failure mechanism. Doing so enables the packaging engineer to design to specific reliability standards, as solder fatigue is a known and predictable failure mechanism. Indeed, other flip chip failure modes such as silicon fracture and underfill delamination are ill-defined in terms of practical failure models, and often lead to unpredictable and early reliability failures.

    Solder fatigue models can serve as valuable tools in predicting and maintaining solder fatigue as a failure mode throughout all stages of flip chip design, qualification and implementation into a production application. A 63Sn/Pb solder fatigue model has been previously developed based on a correlation of flip chip solder fatigue data combined with nonlinear finite element analysis. This model has been successfully applied in the prediction of PBGA and CSP fatigue lives as well as a parametric study investigating the reliability of flip chip assemblies and the influence of specific design parameters. In this investigation, flip chip reliability predictions are generated based on solder fatigue modeling and compared to actual thermal cycling reliability data. The influence of both solder fatigue and underfill delamination are considered in interpretation of the experimental data.

    For the complete document, please contact Hank Carey at hcarey@icinterconnect.com or 719-533-1030 ext121

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