Low Cost Wafer Bumping Processes for Flip Chip Applications (Electroless Nickel-Gold / Stencil Printing)

  • Andrew J.G. Strandjord, Scott F. Popelar, and Curt A. Erickson
    IC Interconnect
    1025 Elkton Drive
    Colorado Springs, CO
    Phone: 719-533-1030
    Fax: 719-533-1021

    This paper describes a wafer bumping process and some of the realities associated with implementing the technology into a high volume production facility. The manufacturing process is based on electroless nickel/gold under-bumpmetallurgy (UBM), stencil based printing of solder/polymer paste, thermal reflow of solders, and automated inspection for yield (bump and die) and bump height/uniformity. Each of these processes is discussed relative to the technology employed, the manufacturing equipment used, and the process controls required to ensure reliable production. Examples of two different devices (9 mil and 17.5 mil pitch) are described in the context of wafer lots going through the manufacturing process within the facility (inquiry to invoice). Bump yields of 99.992% and 100%, with bump heights of 109.8 ìm (3.4 sigma) and 138.3 ìm (2.9 sigma), respectively, were realized for these two devices.

    For the complete document, please contact Hank Carey at hcarey@icinterconnect.com or 719-533-1030 ext121

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