Design Rules for Wafer Bumping

Rev 03


The following document outlines design rules which should be considered when designing a device for a flip chip or chip scale package (CSP) application, or when considering the conversion of a wirebond device to flip chip technology. Designing to these rules will reduce the cost and increase the yields associated with bumping, substrates, assembly, and underfill. As with all design rules, there can be exceptions that may result in various tradeoffs in cost, reliability and/or yield. Each design will be evaluated to ascertain the feasibility of processing with IC Interconnect’s wafer bumping technology


Electroless Ni/Immersion Au UBM

Figure 1 represents the design rules for the electroless plating of the Ni/Au UBM. These rules define the maximum nickel bump height achievable for a given pitch and passivation opening; or conversely, the minimum pitch for a given passivation opening and desired bump height. The rules are fundamentally based on two plating constraints as well as a minimum passivation opening requirement.

  • Constraint 1: Nickel will plate volumetrically in the x-y direction at the same rate as it plates in the z-direction (i.e., thickness direction).
  • Constraint 2: A minimum dimension of 10 µm must be maintained between adjacent plated nickel bumps.

Based on these constraints, the following rules may be derived (see Figure 1 for details):

  • Rule 1: hmax = 0.5 * (PITCH – PO – 10 µm).
  • Rule 2: PITCHmin = (PO + 2h + 10 µm).
  • Rule 3: The minimum passivation opening required to facilitate plating is 25 µm. This rule is based on the minimum amount of exposed aluminum required to activate the electroless plating process.

design guide figure 1 design rules for nickle plating

Figure 1 – Design Rules for Nickel Plating to Avoid Shorting on Nickel Structures

Wafer Passivation

Acceptable wafer passivations include the following:

  • Silicon Nitride
  • Silicon Oxide
  • Silicon Oxynitride
  • SOG (Spin on Glass)
  • Borosilicate Glass
  • Most polyimides
  • BCB

With polyimides, it is recommended that the polyimide be discussed with ICI and tested by ICI to determine compatibility. The most common issue with polyimides is insufficient curing of the film. It is critical that the device’s passivation layer be pin-hole and scratch free. Any exposed final metal will be plated during the bumping process. These passivation layer defects while uncovering a potential reliability issue may also result in a reduction in bumping yield due to the solder wetting to these unexpected plated features.

Saw Streets

Saw streets need to be passivated with silicon nitride or SiO2. Pads in the streets are acceptable but may place constraints on the bump height and/or the sawing of the device. For the case of up to 5 um of e-Ni/Au deposit the pads in the street can be sawn through with some risk of increased edge chipping. For tall e-Ni/Au bumps of = 15 µms it is recommended that the pads in the street be either removed or covered with the device passivation or resist. ICI at this time cannot provide a patterned resist to cover these features.

The acceptable width of the saw street is a function of the dicing process. The ICI design rules for bumping are based on the distance from the bump to the center of the street.

Final Metal Types

Acceptable final metals for the ICI bumping process include:

  • Pure Al
  • AlSi (0.5 to 2.0 % Si)
  • AlCu (0.25 to 2.0 % Cu)
  • AlSiCu
  • Cu (sputtered or plated)

For pure Al and AlSi alloys the minimum acceptable thickness is 2.0 µm. For AlCu and AlSiCu the minimum acceptable thickness is 1.0 µm. Each Al final metal system will be characterized by ICI the first time that the device technology is processed.

Both sputtered and plated Cu final metal can be activated and plated with e-Ni/Au by IC Interconnect. ICI has developed a proprietary seed chemistry that has successfully plated 10 µm passivation openings on a 15 µm pitch with no extraneous plating between the passivation openings or elsewhere on the wafer.

Final Metal Size Relative to Passivation Opening

With the ICI e-Ni/Au bumping process there is no minimum amount of passivation overlap of the final metal pad required. With thin film bumping processes there is a minimum passivation overlap of 16 to 20 µm required to accommodate alignment tolerances, etching processes and the requirement for the UBM to reside completely on top of the final metal pad.

ICI customers have qualified flip chip devices with as little as 2 µm of passivation overlap. This provides greater freedom in the IC design as well as improves the electromigration performance of the device by allowing for greater cross sectional area for the solder bump.

Wafer Thickness

The minimum wafer thickness is a function of wafer size, device technology, bump requirement (i.e., e-Ni/Au only, solder paste or solder ball) and backside surface condition. Minimum wafer thicknesses that have been processed to date are:

  • 150 mm diameter or less – 150 µm
  • 200 mm diameter – 350 µm

For thinner wafers it is required that the wafer be stress relieved to remove all saw damage. The ICI e-Ni/Au bumping process inherently has fewer handling steps than a thin film based bumping process and is therefore capable of processing thinner wafers. However, please consult with ICI regarding your requirement and we will provide guidance for your application.

Backside Finish

Acceptable backside finishes include the following:

  • Oxide
  • Ground Si, with or without stress relief
  • Ag
  • Au

Wafers that have been ground or coated with Au will typically need to be coated with a backside resist during the plating process. Wafers with a silver backside metal may need to be coated with a resist, depending on the Ag deposition process. Please contact ICI if you have any questions on your wafers backside condition.

Fuses

Fuses that are covered by SiO2 can be bumped by ICI. If the fuse has been blown with a laser there is exposed Al and the devices is not suitable for e-Ni/Au bumping.

Device Passivation Openings w/o Solder

Some designs require that not all of the I/O locations be solder bumped for either design or test reasons. The ICI process will protect these openings with an e-Ni/Au UBM that can be probed. These pads can then be left without solder during the solder bumping process. Consult with ICI relative to your specific design requirements.

Solder Bump Formation using Solder Paste Printing

The following describes design rules which define what could be considered an ideal I/O size and layout for wafer bumping a given flip chip design. These guidelines describe rules based on ICI’s stencil printing solder deposition technology. Figure 2 describes dimensions for a peripheral, single row layout, while Figure 3 applies to full array and multiple row I/O designs. ICI recognizes that chip and substrate designers have many additional constraints that may preclude implementation of an optimum bumping design. In such cases, these specific designs will be reviewed in order to determine the feasibility of wafer bumping based on ICI’s technology and an estimate of achievable bump height.

Reflowed solder bump height is a function of the volume of solder deposited as well as the size of the solderable area. The amount of solder which may be printed onto a wafer is in turn a function of the minimum pitch. Table 1 defines the recommended rules for defining X, Y and E as dimensioned in Figure 2 and Figure 3. In addition, no corner bump is allowed for peripheral devices. Note that these design rules may be relaxed as the pitch becomes coarser.
Based upon the above design rules, Table 2 describes recommended passivation openings for some common flip chip pitches, along with achievable bump heights.

Table 1 – Design rules for X, Y and E Dimensions for Solder Paste Bumped Peripheral and Area Array devices.

Design

Design Rule

Definition

Peripheral

X ≥ 1.5*Pitch

X-distance to nearest bump to corner bump

Y ≥ 1.5*Pitch

Y-distance to nearest bump to corner bump

E ≥ Pitch

E-distance from bump to die edge in X or Y

Array(Multiple Row)

E ≥ 0.5*Pitch

E-distance from bump to die edge in X or Y

Table 2 – Design Rules for Recommended Passivation Openings for Common Flip Chip Pitches Utilizing Solder Paste.

Design

Pitch (µm)

Passivation Opening (µm)

Bump Height (µm)

Peripheral

 200

100

100

 250

125

125

>250

Bump Height

0.5 * Pitch

Array(Multiple Row)

 300

100

100

>300

Bump Height

0.33 * Pitch

Currently, IC Interconnect has solder paste bumping production capability for minimum pitches of 200 µm peripheral and 300 µm array. Development efforts are underway to reduce these pitches to 150 and 225 µm, respectively. These efforts are based on a solder transfer technology, details of which are available by contacting ICI.

On the other end of the spectrum, ICI is capable of producing large, CSP-sized solder ball heights (250 to 350 µm) with solder paste or solder spheres depending on bump pitch. As with all designs, a thorough review will be done to fully define achievable bump heights and yields.

preipheral die design for solder bumpingFigure 2 – Peripheral Die Design for Solder Bumping

Area Array (Multiple Row Design) for Solder Bumping

Figure 3 – Area Array (Multiple Row Design) for Solder Bumping

Solder Ball Formation (Based on Ball Drop Technology)

Solder paste is approximately 50 percent solder by volume. With solder paste a general guideline is that the achievable reflowed solder bump heights will typically be one half of the pitch for peripheral designs, and one third of the pitch for array designs.

For applications where large solder bump heights are required, it may be necessary to utilize preformed solder spheres. This allows for reflowed bump heights of approximately one half the bump pitch for array devices. (Note that because of the nature of dropping spheres, peripheral designs are the same as array designs as far as processing constraints are concerned.)

The ICI WLP technology does not support a redistribution technology. As many products in WLPs today are designed with a “Bump on I/O” structure, they are well suited for the ICI WLP process. Many products that are “Bump on I/O” structures and were originally designed for a thin film based WLP process can be directly converted to the ICI WLP technology.

Many standard CSP applications involve footprints on a 500 µm pitch. For these 500 µm pitch designs, it is typical to deposit 300 µm spheres. The wafer bumping design rules for these types of applications are then straight forward:

  • Keep the pitch between die greater or equal to the pitch within a die. Based on this rule, Table 3 defines the geometries as dimensioned in Figure 2 and Figure 3.

Corresponding bump heights are then dependent on the passivation opening. Ideally for the best reliability and process optimization, the passivation opening will be designed between 200 and 220 µm in diameter. Table 4 summarizes corresponding bump heights for this passivation opening range. For example, a 300 µm sphere dropped on a 500 µm pitch produces a reflowed solder bump height of approximately 250 µm for a 220 µm passivation opening.

Table 3 – Ball Drop design rules for E (refer to Figure 3)

Design

Design Rule

Definition

Array(Multiple Row)

E ≥ 0.5*Pitch

E-distance from bump to street C/L in X or Y

Table 4 – Design Rules for Recommended Passivation Openings for Wafer Level Package Designs Utilizing 300 µm Solder Balls on 500 µm Pitch.

Design

Pitch (µm)

Passivation Opening (µm)

Bump Height (µm)

Array

500

200

260

500

210

255

500

220

250

Each ball drop application will be reviewed and evaluated to determine its compatibility with ICI’s wafer bumping technology. Process development is currently focused on dropping 250 µm spheres on 400 µm pitch footprints.

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