Solder Bumping/ Printing

Solder Printing


Once the electroless nickel/gold UBM has been established, the next step in the wafer bumping process is solder deposition. One of the most cost-effective methods available is printing solder paste on the I/O pads utilizing stencil technology. This entails manufacturing a stencil that contains apertures that will align with the I/O pads across the wafer.

Solder is transferred through the stencil to the wafer by pushing a bead of solder paste across the stencil with a squeegee blade or using one of several extrusion technologies which are now available. Although routine for surface mount applications, early attempts at stencil printing solder onto wafers failed due to limitations in stencil and solder paste technology. The dimensions and tolerance control required for wafer bumping stencils, along with fine mesh solder paste, did not exist. However, recent developments in fine geometry stencils and Type V and VI solder pastes have made solder printing a viable option for solder deposition of wafers. Also worth noting is the applicability of this technique toward applying isotropic polymers on top of the Ni/Au under-bump- metallurgy.

Solders currently available from IC Interconnect:

  • Eutectic Solder (37/63 PbSn)
  • High Lead Solder (90/10 PbSn)
  • Lead-Free Solder (SnAgCu)
  • Conductive Epoxies

Stencil Fabrication

To date, three general methods exist for stencil fabrication: chemical etching, laser cutting, and nickel plate-up. While all three have their advantages when it comes to producing canadian pharmacy stencils for circuit board manufacturing, not all are suitable for generating wafer bumping stencils. Chemical etching cannot support the fine geometries and tolerances required for wafer bumping stencils, and is not generally considered as a viable process for producing these stencils.

For stencils made using the laser cutting process, a foil is held flat while the apertures are cut with a high power laser. The observed tight tolerances on aperture dimensions, combined with the smooth sidewalls, make laser cutting stencils a desirable process. However, the cost of laser cut stencils increases with the number of apertures. Nonetheless, for devices with relative low I/O counts (<50,000 I/O), laser cutting stencils are a viable option, especially for fine pitch devices.

The third method for generating stencils is the nickel plate-up process, where the stencil is grown by plating nickel onto a mandrel through a patterned dry film resist. This process also produces smooth aperture sidewalls with tight tolerances on shape and size. Through utilization of nickel plate-up, all apertures are produced at the same time, making the cost of a 10,000 aperture stencil the same as a 500,000 aperture stencil . The combination of low cost per aperture, tight tolerances, and smooth surface finish makes nickel plate-up the most promising method for creating wafer bumping stencils [6].

Optical micrographs of wafer bumping stencils (Photo Stencil Inc.):

Laser cut stencil

Laser cut stencil

(3 mil Alloy-42, 6×18 mil oblongs)

Plate-up stencil

Plate-up stencil

(3 mil nickel, 6×18 mil oblong)

The printer variables that have an affect on paste volume transfer and uniformity, include print pressure, print speed, print gap, separation speed between the stencil and the wafer, and print application technique (squeegee or extrusion). The system used in this application is a modified DEK 265Lt printer.

For solder bumping based on stencil printing to be feasible, consistent and sufficient solder paste volume must be transferred to the wafer. Often times, aperture size and shape will be limited by the die I/O layout in terms of pad size, pitch, and perimeter versus array I/O devices. Hence, there may be certain bounds to the amount of paste that can be deposited for particular die designs.

Stencil printing of solder for flip chip applications has many desirable attributes, including:

  1. its versatility in applying many different alloys and even polymers,
  2. the process does not require any lithography or thin film steps, and
  3. it is relatively very low cost.


image017Modified DEK 265Lt surface mount printer Type V solder paste. Fine pitch stencil technology.

Critical variables:

1) Stencil Parameters 
        Consistent aperture shapes and sizes
        Smooth aperture sidewalls
        Consistent paste release
2) Print Pressure
3) Print Speed
4) Print Gap
5) Separation Speed 
6) Squeegee Blade or Extrusion Head 
7) Paste (Type V eutectic lead/tin solder paste)
        Paste Viscosity
        Paste Loading

Peripheral Array Printing

Typical specification for solder bump height relative to pad pitch:

Pad Pitch

Solder Bump Height


70 um








Full Array Solder Printing

7x7 mil Stencil Printed

7×7 mil Stencil Printed

Solder on 9 mil Pitch

Discrete Component Bumping (DCB)

Solder paste deposits

Solder paste deposits

5 mil reflowed solder

5 mil reflowed solder

Discrete Component Bumping (DCB) 5 x 15 mil rectangular I/O pads.

Chip Scale Packaging (CSP)

FlipFet before Bumping

FlipFet before Bumping

FlipFet after Bumping

FlipFet after Bumping


Multiple Reflows

Eutectic : High Lead : Lead Free Solders


Eutectic solder bumps

PbSn (37/63)
210 degC peak reflow temperature
Solder Height  (~110 um)
Pad Area = 37.75 sq. mil
Failure Mode = Bulk Solder

High lead solder bumps

PbSn (90/10) 
330 degC peak reflow temperature
Solder Height  (~110 um)
Pad Area = 37.75 sq. mil
Failure Mode = Bulk Solder

Lead Free solder bumps

SnAgCu (95.5/3.8/0.7)
250 degC peak reflow temperature
Solder Height  (~110 um)
Pad Area = 37.75 sq. mil
Failure Mode = Bulk Solder

High Lead with 1, 2, 5 um of Nickel UBM

1 um of Electroless Nickel/Gold UBM

2 um of Electroless Nickel/Gold UBM

5 um of Electroless Nickel/Gold UBM

Solder Reflow

The reflow process and conditions are essential for generating smooth, spherical solder bumps, with minimal void content.


The factors that affect these attributes include: 

  1. atmospheric conditions (i.e., residual oxygen content),
  2. heating mechanism (convection, conduction, or radiation),
  3. heating rate, and
  4. absolute temperature. 

A Sikama Falcon 8x5C reflow oven purged with nitrogen is used for the reflow process. Flux removal is accomplished via a DI wafer soak, followed by spin rinse cycling and a nitrogen dry.


Void Analysis

The following chart shows the effect of five different reflow profiles on void content and size. The presence and size of the voids was detected via x-ray analysis. A general rule of thumb for void occurrence is that one does not want to observe voids that are greater than ¼ the diameter of the bump. Profile 3 yields no voids greater than ¼ of the bump diameter, and also yields the lowest number of overall voids.

Chart of voids vs reflow profile:


Multiple Reflow vs Adhesion/Shear(Eutectic Solder)

The following figures show the effect of multiple solder reflows on solder adhesion for two different Flip Chip designs, FC1 and FC2, respectively. Note that there is no degradation shear strength due to multiple reflows. Furthermore, no shift in failure mode from the bulk solder was observed.

Flip Chip Design One (FC1)

9 mil pitch 68 I/O per die 295 die/wafer (13X magnification)

9 mil pitch
68 I/O per die
295 die/wafer
(13X magnification)

6.5 mil bond pads

6.5 mil bond pads

Flip Chip Design Two (FC2)

17.5 mil min pitch 18 I/O per die 1,246 die/wafer (26X magnification)

17.5 mil min pitch
18 I/O per die
1,246 die/wafer
(26X magnification)

4.0 mil rd bond pads

4.0 mil rd bond pads

Wafer Bumping and Related Services

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